hdlbits答案：Bugs mux2、Bugs nand3、Gates4、Vector3、Vector4、Vector5

2023-10-17 06:00| 来源: 网络整理| 查看: 265

注：前面两个题是hdlbits中靠后的两道题目，目录是verification→finding bugs in code→mux 、nand。

This 8-bit wide 2-to-1 multiplexer doesn't work. Fix the bug(s).

module top_module ( input sel, input [7:0] a, input [7:0] b, output [7:0]out ); assign out = (sel?a:b); endmodule

就是一个选择器，所以索性不要按照给出的复杂或逻辑去实现，用assgin判一下sel信号的高低就好。

--------------------------------------------------------------------------------------------------------------------------

This three-input NAND gate doesn't work. Fix the bug(s).

You must use the provided 5-input AND gate:

module andgate ( output out, input a, input b, input c, input d, input e ); module top_module (input a, input b, input c, output out);// wire out_q; andgate inst1 (out_q, a, b, c, 1'b1,1'b1); assign out=~out_q; endmodule

注意审题，题目给出的是5输入的与门，但是要输出的是三输入的与非门，所以需要中间变量assign 一下。

=========================================================================

Build a combinational circuit with four inputs, in[3:0].

There are 3 outputs:

out_and: output of a 4-input AND gate.out_or: output of a 4-input OR gate.out_xor: output of a 4-input XOR gate. module top_module( input [3:0] in, output out_and, output out_or, output out_xor ); assign out_and=∈ assign out_or =|in; assign out_xor=^in; endmodule

使用按位逻辑，代码更简洁。

-----------------------------------------------------------------------------------------------------------------

A Bit of Practice

Given several input vectors, concatenate them together then split them up into several output vectors. There are six 5-bit input vectors: a, b, c, d, e, and f, for a total of 30 bits of input. There are four 8-bit output vectors: w, x, y, and z, for 32 bits of output. The output should be a concatenation of the input vectors followed by two 1 bits:

module top_module ( input [4:0] a, b, c, d, e, f, output [7:0] w, x, y, z );// assign {w,x,y,z}={a,b,c,d,e,f,2'b11}; endmodule -------------------------------------------------------------------------------------------- A Bit of Practice

One common place to see a replication operator is when sign-extending a smaller number to a larger one, while preserving its signed value. This is done by replicating the sign bit (the most significant bit) of the smaller number to the left. For example, sign-extending 4'b0101 (5) to 8 bits results in 8'b00000101 (5), while sign-extending 4'b1101 (-3) to 8 bits results in 8'b11111101 (-3).

Build a circuit that sign-extends an 8-bit number to 32 bits. This requires a concatenation of 24 copies of the sign bit (i.e., replicate bit[7] 24 times) followed by the 8-bit number itself.

module top_module ( input [7:0] in, output [31:0] out );// assign out={ { 24{in[7]} }, in}; endmodule

这个题说难也难，说简单也简单，提交了三次，其实就是 {} 符号没有加够，需要仔细回味拼接的妙用。

Vector5

As the diagram shows, this can be done more easily using the replication and concatenation operators.

The top vector is a concatenation of 5 repeats of each inputThe bottom vector is 5 repeats of a concatenation of the 5 inputs

很满意的一段代码，如果不优化，写出来的很长

module top_module ( input a, b, c, d, e, output [24:0] out );// wire [24:0]A,B; assign A={ {5{a}},{5{b}},{5{c}},{5{d}},{5{e}} }; assign B={ {5{a,b,c,d,e}} }; assign out =~(A^B); endmodule

【本文地址】

公司简介

联系我们